1. Field of the Invention
This invention generally relates to a method for manufacturing a semiconductor device and its resulting structure, and in particular to a method for manufacturing a semiconductor device having both bipolar and MOS transistors on the same substrate according to a standard cell scheme and its resulting structure.
2. Description of the Prior Art
A standard cell scheme is a design method for realizing a semiconductor integrated circuit device having a desired logic function by using a library of standard cells which have been previously designed manually or by an electronic computer and verified. In accordance with such a standard cell method, mainly semiconductor integrated circuit devices including MOS transistors have been manufactured. In custom ICs, semiconductor integrated circuit devices having both analog circuits and digital circuits are required. In designing such custom ICs, bipolar transistor sections are not in the form of standard cell format.
FIG. 2 illustrates a typical prior art Bi-CMOS semiconductor integrated circuit device having both bipolar and CMOS transistors. As shown, the illustrated structure includes a P type silicon substrate 1 on which a P type epitaxial layer 2 is formed. In the region where a bipolar NPN transistor is formed, an N.sup.+ type buried layer 3 is formed between the substrate 1 and the epitaxial layer 2. In the region where an NPN transistor is formed, an N type well 4a is formed as a collector and a P type base 7 is formed within the well 4a with an N type emitter 8 being formed within the base 7 to thereby define an NPN transistor 15. In the region where a PMOS transistor is formed, an N type well 4b is formed in the epitaxial layer 2 and a pair of P.sup.+ type diffusion regions 6, 6 is formed at the surface of the well 4b with a gate electrode 10a comprised of a polysilicon layer being formed above a channel region with a gate oxide film sandwiched therebetween to thereby define a PMOS transistor 14. In the region where an NMOS transistor is formed, a pair of N.sup.+ type diffusion regions 5, 5 is formed at the surface of the epitaxial layer 2 and a gate electrode 10b is formed from a polysilicon layer above a channel region with a gate oxide film sandwiched therebetween to thereby define an NMOS transistor 13. Also shown in FIG. 2 are a field oxide film 9, a PSG film 11 and an aluminum interconnection 12.
In a semiconductor integrated circuit device having both analog and digital circuits as shown in FIG. 2, a supply voltage for an analog circuit section including the bipolar transistor 15 may differ from a supply voltage for a digital circuit section including the NMOS and PMOS transistors 13 and 14. For example, the supply voltage for the analog circuit may be .+-.5V, whereas the supply voltage for the digital circuit may be in the range between -5V and 0V. In the case of exchanging data between such a semiconductor integrated circuit device and another digital semiconductor integrated circuit device, since digital semiconductor integrated circuit devices are normally operated at the voltage ranging from 0V to 5V, there arises a problem because of a discrepancy in the supply voltage between the two semiconductor integrated circuit devices.
In such a case, use has been conventionally made of a level shifter to shift the voltage level of a signal to match the voltage levels between the respective signals. However, the provision of such a level shifter tends to slow down the overall operation and thus it tends to limit the high speed operation. In addition, the provision of such a level shifter also occupies an area on the substrate, which tends to lower the degree of integration in a semiconductor integrated circuit device.
In a semiconductor device having both bipolar and MOS transistors, since power supply voltages typically differ between the two, even if the MOS transistor section has been conventionally formed in a standard cell format, there is a difficulty in forming the bipolar transistor section in the form of a standard cell format in a manner similar to a cell library of MOS transistors. Thus, there has not been proposed to design a Bi-CMOS custom IC according to a full standard cell scheme. As a result, the bipolar transistor section must be designed and fabricated according to an individual custom design method, so that designing and fabrication of a Bi-CMOS custom IC tends to be time consuming and expensive. In addition, since use cannot be made of verified cells in fabrication, the yield also tends to be lower.